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Summary: Partitioning Multi-Threaded Processors with a Large Number of Threads £
Ali El-Moursy , Rajeev Garg , David H. AlbonesiÝ
and Sandhya Dwarkadas
Departments of Electrical and Computer Engineering and of Computer Science, University of Rochester
Ý
Computer Systems Laboratory, Cornell University
elmours@ece.rochester.edu, garg,sandhya @cs.rochester.edu, albonesi@csl.cornell.edu
Abstract
Today's general-purpose processors are increasingly us-
ing multithreading in order to better leverage the additional
on-chip real estate available with each technology genera-
tion. Simultaneous Multi-Threading (SMT) was originally
proposed as a large dynamic superscalar processor with
monolithic hardware structures shared among all threads.
Intel's Hyper-Threaded Pentium 4 processor partitions the
queue structures among two threads, demonstrating more
balanced performance by reducing the hoarding of struc-
tures by a single thread. IBM's Power5 processor is a 2-way
Chip Multiprocessor (CMP) of SMT processors, each sup-
porting 2 threads, which significantly reduces design com-
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