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Eager meets Lazy: the Impact of Write-Buffering on Hardware Transactional Memory
 

Summary: Eager meets Lazy: the Impact of Write-Buffering
on Hardware Transactional Memory
Anurag Negi Rub´en Titos-Gil Manuel E. Acacio Jos´e M. Garc´ia Per Stenstrom
Chalmers University of Technology
Universidad de Murcia
{negi,per.stenstrom}@chalmers.se
{rtitos,meacacio,jmgarcia}@ditec.um.es
Abstract--Hardware transactional memory (HTM) systems
have been studied extensively along the dimensions of speculative
versioning and contention management policies. The relative
performance of several designs policies has been discussed at
length in prior work within the framework of scalable chip-
multiprocessing systems. Yet, the impact of simple structural
optimizations like write-buffering has not been investigated and
performance deviations due to the presence or absence of these
optimizations remains unclear. This lack of insight into the
effective use and impact of these interfacial structures between
the processor core and the coherent memory hierarchy forms the
crux of the problem we study in this paper. Through detailed
modeling of various write-buffering configurations we show that

  

Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences