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Summary: HARDWARE AND SOFTWARE MECHANISMS
FOR REDUCING LOAD LATENCY
By
Todd Michael Austin
A dissertation submitted in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy
(Computer Sciences)
at the
UNIVERSITY OF WISCONSIN { MADISON
1996
i
Abstract
As processor demands quickly outpace memory, the performance of load instructions becomes an
increasingly critical component to good system performance. This thesis contributes four novel load
latency reduction techniques, each targeting a di erent component of load latency: address calculation,
data cache access, address translation, and data cache misses. The contributed techniques are as
follows:
Fast Address Calculation employs a stateless set index predictor to allow address calculation to
overlap with data cache access. The design eliminates the latency of address calculation for many
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