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Summary: Remora: A Dynamic Self-Tuning Processor
Chris Weaver, Fadi Gebara, Todd Austin, and Richard Brown
Designed as part of EECS 627 (VLSI II) at the University of Michigan
Abstract
This paper describes a self-tuning architecture that dynamically adjusts the frequency of the processor to run
at the highest speed it can sustain without causing errors. This frequency is determined through dynamic verifica-
tion, an online error checking technique that uses a second, simpler processor to redundantly execute instructions,
detecting both design errors and transient faults.
hAbstract
This paper describes a self-tuning architecture that dynam-
ically adjusts the frequency of the processor to run at the high-
est speed it can sustain without causing errors. This frequency
is determined through dynamic verification, an online error
checking technique that uses a second, simpler processor to
redundantly execute instructions, detecting both design errors
and transient faults.
1 Introduction
1.1 Dynamic Verification
To implement dynamic verification, a microprocessor is
constructed using two heterogeneous internal processors that
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