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Summary: 1. This research is supported by DARPA under Contract No.
DABT63-96-C-0074. The results presented herein do not neces-
sarily reflect the position or the policy of the U.S. Government.
Digest of Papers: IEEE International High-Level Design Validation and Test Workshop, 1997, pp. 194-201.
High-Level Design Verification of Microprocessors via Error Modeling1
Hussain Al-Asaad, David Van Campenhout, John P. Hayes, Trevor Mudge, and Richard B. Brown
Advanced Computer Architecture Laboratory
Department of Electrical Engineering and Computer Science
The University of Michigan, Ann Arbor, MI 48109-2122
E-mail: {halasaad, davidvc, jhayes, tnm, brown}@eecs.umich.edu
Abstract
A project is under way at the University of Michigan to
develop a design verification methodology for micropro-
cessor hardware based on modeling design errors and
generating simulation vectors for the modeled errors via
physical fault testing techniques. We have developed a
method to systematically collect design error data, and
gathered concrete error data from a number of micropro-
cessor design projects. The error data are being used to
derive error models suitable for design verification testing.
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