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Summary: Bulk Disambiguation of Speculative Threads in Multiprocessors
Luis Ceze, James Tuck, Calin Cas¸caval
and Josep Torrellas
University of Illinois at Urbana-Champaign
{luisceze, jtuck, torrellas}@cs.uiuc.edu
http://iacoma.cs.uiuc.edu
IBM T.J. Watson Research Center
cascaval@us.ibm.com
Abstract
Transactional Memory (TM), Thread-Level Speculation (TLS),
and Checkpointed multiprocessors are three popular architectural
techniques based on the execution of multiple, cooperating specu-
lative threads. In these environments, correctly maintaining data de-
pendences across threads requires mechanisms for disambiguating
addresses across threads, invalidating stale cache state, and making
committed state visible. These mechanisms are both conceptually
involved and hard to implement.
In this paper, we present Bulk, a novel approach to simplify these
mechanisms. The idea is to hash-encode a thread's access informa-
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