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Instruction Issue and Data Forwarding Mechanisms for Asynchronous Superscalar Processors
 

Summary: Instruction Issue and Data Forwarding Mechanisms for Asynchronous
Superscalar Processors
D.K. Arvind and R.D. Mullins y
Division of Informatics
The University of Edinburgh
Mayfield Road, Edinburgh EH9 3JZ, Scotland.
dka@dcs.ed.ac.uk or Robert.Mullins@cl.cam.ac.uk
Abstract
An asynchronous design methodology
offers potential advantages for architectures
implemented in deep sub­micron technologies,
such as low power dissipation and good
electro­magnetic compatibility. This paper
explores the impact of such a methodology on
the architecture of superscalar processors. We
examine in particular out­of­order instruction
issue and data forwarding in the absence of
global synchronisation. Three schemes are
presented, and the performances of the resulting
asynchronous superscalar architectures are

  

Source: Arvind, D. K. - School of Informatics, University of Edinburgh

 

Collections: Computer Technologies and Information Sciences