Summary: RealTime Scheduling on Multicore Platforms (Full Version) #
James H. Anderson, John M. Calandrino, and UmaMaheswari C. Devi
Department of Computer Science
The University of North Carolina at Chapel Hill
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher pro
cessor performance, given that thermal and power problems impose limits on the performance of singlecore designs. Accordingly,
several chip manufacturers have already released, or will soon release, chips with dual cores, and it is predicted that chips with up to
32 cores will be available within a decade. To effectively use the available processing resources on multicore platforms, software
designs should avoid coexecuting applications or threads that can worsen the performance of shared caches, if not thrash them.
While cacheaware scheduling techniques for such platforms have been proposed for throughputoriented applications, to the best of
our knowledge, no such work has targeted realtime applications. In this paper, we propose and evaluate a cacheaware Pfairbased
scheduling scheme for realtime tasks on multicore platforms.
Keywords: Multicore architectures, multiprocessors, realtime scheduling.
# Work supported by NSF grants CCR 0309825 and CNS 0408996. The third author was also supported by an IBM Ph.D. fellowship.
Thermal and power problems limit the performance that singleprocessor chips can deliver. Multicore architectures, or chip multi
processors, which include several processors on a single chip, are being widely touted as a solution to this problem. Several chip