Summary: Real­Time Scheduling on Multicore Platforms (Full Version) #
James H. Anderson, John M. Calandrino, and UmaMaheswari C. Devi
Department of Computer Science
The University of North Carolina at Chapel Hill
October 2005
Abstract
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher pro­
cessor performance, given that thermal and power problems impose limits on the performance of single­core designs. Accordingly,
several chip manufacturers have already released, or will soon release, chips with dual cores, and it is predicted that chips with up to
32 cores will be available within a decade. To effectively use the available processing resources on multicore platforms, software
designs should avoid co­executing applications or threads that can worsen the performance of shared caches, if not thrash them.
While cache­aware scheduling techniques for such platforms have been proposed for throughput­oriented applications, to the best of
our knowledge, no such work has targeted real­time applications. In this paper, we propose and evaluate a cache­aware Pfair­based
scheduling scheme for real­time tasks on multicore platforms.
Keywords: Multicore architectures, multiprocessors, real­time scheduling.
# Work supported by NSF grants CCR 0309825 and CNS 0408996. The third author was also supported by an IBM Ph.D. fellowship.

1 Introduction
Thermal and power problems limit the performance that single­processor chips can deliver. Multicore architectures, or chip multi­
processors, which include several processors on a single chip, are being widely touted as a solution to this problem. Several chip

Source: Anderson, James - Department of Computer Science, University of North Carolina at Chapel Hill

Collections: Computer Technologies and Information Sciences