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Scan Test of IP Cores in an ATE Environment L.Schiano, Y.B.Kim, F.Lombardi
 

Summary: Scan Test of IP Cores in an ATE Environment
L.Schiano, Y.B.Kim, F.Lombardi
Department of Electrical and Computer Engineering
Northeastern University
Boston MA 02115
Abstract
Manufacturing test of chips made of multiple IP cores
requires different techniques if ATE is used. As scan chains
are commonly used as access paths to the DUT, ATE ar-
chitectures must be designed to facilitate this arrangement.
An increase in ATE performance for scan test requires a re-
duction in both scan time and memory utilization as com-
monly used figures of merit; in this paper, an ATE hard-
ware architecture that allows the scan test to be done in
an "interleaved" mode (thus separating the Scan-In and
Scan-Compare sequences), is utilized together with a novel
test scheduling algorithm. Two variations of the algorithm
which permit test reordering and merging as well as an ef-
ficient generation of the so-called monolithic test sequence
are proposed. Scheduling is found in polynomial time com-

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering