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Low-Power Implementation ofFIR Filters within an Adaptive Reconfigurable Architecture
 

Summary: Low-Power Implementation ofFIR Filters within an
Adaptive Reconfigurable Architecture
Evangelos F. Stefatos', Ilias Bravos2 and Tughrul Arslan" 2
'School ofEngineering & Electronics,
King's Buildings, Mayfield Rd, EH9 3JL, Scotland, UK
2Institute for System Level Integration,
Alba Centre, Alba Campus, Livingston, EH54 7EG, Scotland, UK
Evangelos.Stefatos@ee.ed.ac.uk
Abstract-This paper presents a custom Very-Large-Scale- method is based on the creation of look-up-tables (LUTs) for
Integration architecture, which consists of a reconfigurable storing the description of the multiplier graphs. Hence, this
hardware substrate and a hybrid-genetic algorithm responsible method is inefficient even for coefficients smaller than 12
for resolving the optimal configuration for the reconfigurable bits, since huge amount of memory must be available in the
components of the substrate. The reconfigurable hardware is system. An improvement in MAG algorithm is presented in
specifically tailored for the implementation of multiplier-less [4] (RAG-n), which is a combination ofMAG and a heuristic
symmetrical Finite-Impulse-Response filters based on the algorithm. In this paper we present a genetically based
primitive operator technique, while the architecture of the
. ' . . . ~~~methodology for the implementation of low-power
hybrid-genetic algorithm aims to improving the quality of the multiplier-less FIR filters within a custom reconfigurable
realized filters and speeding-up the time required for their architecture. The created filters present numerous advantagesrealization. Power analysis demonstrates that the filters, which suchitstreducedpow
ersuption, numeroushadvandare implemented by our architecture, consume considerably such as reduced power consumption, high-throughput and

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering