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Summary: Appears in the Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001)
Exploring the Design Space of Future CMPs
Jaehyuk Huh Stephen W. Keckler Doug Burger
Computer Architecture and Technology Laboratory
Department of Computer Sciences
The University of Texas at Austin
cart@cs.utexas.edu -- www.cs.utexas.edu/users/cart
Abstract
In this paper, we study the space of chip multiproces-
sor (CMP) organizations. We compare the area and per-
formance trade-offs for CMP implementations to determine
how many processing cores future server CMPs should
have, whether the cores should have in-order or out-of-
order issue, and how big the per-processor on-chip caches
should be. We find that, contrary to some conventional
wisdom, out-of-order processing cores will maximize job
throughput on future CMPs. As technology shrinks, limited
off-chip bandwidth will begin to curtail the number of cores
that can be effective on a single die. Current projections
show that the transistor/signal pin ratio will increase by a
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