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Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture
 

Summary: Defect-Tolerant Gate Macro Mapping & Placement in
Clock-Free Nanowire Crossbar Architecture
Ravi Bonam1
, Yong-Bin Kim2
and Minsu Choi1
1
Dept of ECE, University of Missouri-Rolla, Rolla, MO 65409-0040, USA
{rkbcdf, choim}@umr.edu
2
Dept of ECE, Northeastern University, Boston, MA 02115, USA
ybk@ece.neu.edu
Abstract
Recently, we proposed a new clock-free nanowire crossbar architecture based on a delay-
insensitive paradigm called Null Convention Logic (NCL). The proposed architecture has
simple periodic structure that is suitable for non-deterministic nanoscale assembly and does
not require a clock distribution network - so it is intrinsically free from timing-related failure
modes. Even though the proposed architecture offers improved manufacturability, it is still
not free from defects. This paper elaborates on the different programming techniques to map
a given threshold gate macro on a random PGMB (Programmable Gate Macro Block) with
predefined dimension. Defect-Aware and Defect Unaware approaches have been considered

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering