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Parallel-Stage Decoupled Software Pipelining Easwaran Raman Guilherme Ottoni Arun Raman
 

Summary: Parallel-Stage Decoupled Software Pipelining
Easwaran Raman Guilherme Ottoni Arun Raman
Matthew J. Bridges David I. August
Departments of Computer Science and Electrical Engineering
Princeton University
{eraman, ottoni, rarun, mbridges, august}@princeton.edu
ABSTRACT
In recent years, the microprocessor industry has embraced chip
multiprocessors (CMPs), also known as multi-core architectures,
as the dominant design paradigm. For existing and new applica-
tions to make effective use of CMPs, it is desirable that compilers
automatically extract thread-level parallelism from single-threaded
applications. DOALL is a popular automatic technique for loop-
level parallelization employed successfully in the domains of scien-
tific and numeric computing. While DOALL generally scales well
with the number of iterations of the loop, its applicability is lim-
ited by the presence of loop-carried dependences. A parallelization
technique with greater applicability is decoupled software pipelin-
ing (DSWP), which parallelizes loops even in the presence of loop-
carried dependences. However, the scalability of DSWP is limited

  

Source: August, David - Department of Computer Science, Princeton University

 

Collections: Computer Technologies and Information Sciences