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Summary: Probabilistic Analysis of Design Mapping in
Asynchronous Nanowire Crossbar Architecture
Shikha Chaudhary and Minsu Choi
Dept of Electrical & Computer Engineering
Missouri University of Science & Technology
Rolla, MO 65409
Email: {sc8tc, choim}@mst.edu
Yong-Bin Kim
Dept of Electrical & Computer Engineering
Northesastern University
Boston, MA, 02115
Email: ybk@ece.neu.edu
Abstract--There have been numerous nanowire crossbar ar-
chitectures proposed till date and they are envisioned as clock-
driven. To deal with numerous issues caused by clocking, a
new asynchronous architecture based on Null Convention Logic
(NCL) has been recently proposed, resulting in the removal
of the clock circuit overhead from the crossbar architecture.
The proposed architecture is easier to be manufactured and
all clocking-related issues are also eliminated. Even though the
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