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IMTC 200.1 -InsUumrntauonand Measurement Technology Conference

Summary: IMTC 200.1 - InsUumrntauonand Measurement
Technology Conference
C O ~ O ,MY, tx-20,200~
Timing Requirement for Reliable Latch-BasedCircuit Design
Young Jun Lee', Yong-Bin Kim', E Lombardi', Nohpill Park'
ECE D e p ~ ~ ~ ~ c n t .
Nonheaslent University,
Boston M A 021 15. USA
E-mail: {yjlee, ybk, lomhardi)@ece.ncu.edu
'Oklahoma Stare University,
Stillwnler OK 74078. USA
Emsil: nparkkecs.oksta1e.cdu
As performance target gets faster and interconnect delays
increase as fahncation technology dcvelops, thc penalty that
clock skew imposes on cycle time becomes more costly. The
cycle time overhead of clock uncertainty can be eliminated in
the latch-based design if the circuit delays between latches are
balanced. Furthermore, latches provide more tlexihility for
tuning the stagcs of a pipeline or manipulating timing hud-


Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University


Collections: Engineering