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On the Evaluation of Dense Chip-Multiprocessor Architectures

Summary: On the Evaluation of Dense Chip-Multiprocessor
Francisco J. Villa, Manuel E. Acacio, José M. García
Departamento de Ingeniería y Tecnología de Computadores
University of Murcia, 30080 Murcia (Spain)
Email: {fj.villa,meacacio,jmgarcia}@ditec.um.es
Abstract-- Chip-multiprocessors (CMPs) have been revealed
as the most promising way of making efficient use of current
improvements in integration scale. Nowadays, commercial CMP
releases integrate at most 8 processor cores onto the chip.
However, 16 or more processor cores are expected to be offered
in near future Dense-CMP (D-CMP) systems. In this way, these
architectures impose new design restrictions, and some topics,
such as the cache-coherence problem, must be reviewed.
In this paper we present an exhaustive performance evaluation
of two recently proposed D-CMP architectures, making special
emphasis on the solution to the cache-coherence problem that
each one of them introduces. The Shared Bus Fabric architecture
(SBF) features a snoop cache-coherence protocol and is based
on a high-performance bus fabric interconnection network. The


Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia


Collections: Computer Technologies and Information Sciences