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ELECTRONICS LETTERS 10th December 1998 Vol. 34 No. 25 Low power DCT implementation approach
 

Summary: ELECTRONICS LETTERS 10th December 1998 Vol. 34 No. 25
Low power DCT implementation approach
for CMOS­based DSP processors
S. Masupe and T. Arslan
An algorithm is presented for the low power implementation of the
discrete cosine transform on single multiplier CMOS DSPs. The
algorithm reduces power by reducing the amount of switched
capacitance within the multiplier section of the DSP. This is
achieved by a combination of using shift operations where possible,
and manipulating bit­correlation between successive cosine
coefficients applied to the input of the multiplier section. It is shown
with a number of examples that up to 50% power saving can be
achieved and that the algorithm provides a potential for more
savings in power.
Introduction: Recently there has been a considerable interest in the
low power implementation of the discrete cosine transform (DCT).
This is mainly due to the DCT being the computational bottleneck
of standards such as JPEG and MPEG [1]. Most research work con­
sidering the low power implementation of the DCT has targeted
reducing the computational complexity of its design or modifying

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering