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The RAMP Architecture & Description Language Greg Gibeling, Andrew Schultz & Krste Asanovic
 

Summary: The RAMP Architecture & Description Language
Greg Gibeling, Andrew Schultz & Krste Asanovi´c
RAMP Gateware Group, UC Berkeley & MIT CSAIL
{gdgib & alschult}@eecs.berkeley.edu, krste@csail.mit.edu
January 17, 2006
1 Introduction
The RAMP (Research Accelerator for Multiproces-
sors) project is developing infrastructure to sup-
port high-speed emulation of large scale, massively
parallel multiprocessor systems using FPGA plat-
forms. In this paper, we describe our proposal
for a RAMP Design Framework (RDF), which has
a number of challenging goals. The framework
must support both cycle-accurate emulation of de-
tailed parameterized machine models and rapid
functional-only emulations. The framework should
hide changes in the underlying RAMP hardware
from the module designer as much as possible, to
allow groups with different hardware configurations
to share designs and to allow RAMP modules to be

  

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

 

Collections: Computer Technologies and Information Sciences