 
Summary: IEE Electronics Letters, vol. 34, no. 19, pp. 18171819, 1998.
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A Lowpower Coefficient Segmentation Algorithm for FIR Filter Implementation
A.T. Erdogan and T. Arslan
Cardiff University of Wales
Cardiff School of Engineering
Cardiff CF2 3TF
United Kingdom
Indexing terms: Low power, Digital Signal Processing,, FIR filters
Abstract: A new multiplication algorithm is introduced for lowpower implementation of digital filters on
CMOS based digital signal processing systems. The algorithm decomposes individual coefficients into two less
complex subcomponents. The decomposition, performed using a heuristic approach, divides a given coefficient
such that a part is produced which can be implemented using a single shift operation leaving another part with a
reduced wordlength to be applied to the coefficient input of the hardware multiplier. This results in a significant
reduction in the amount of switched capacitance and consequently power consumption. The paper describes the
algorithm, presents associated results, including effects of overheads due to shift operations, showing up to 63%
saving in power.
Introduction: Due to the surge in portable computing industry, there is a continuous demand for effective methods of
implementing commonly used computationally intensive DSP tasks such as digital filtering. One way of reducing the
power consumption of digital filters, is to reduce the amount of switched capacitance during its operation. Example
