Summary: 1
Adaptive Cache Memories
for SMT Processors
Sonia Lopez, Oscar Garnica, David H. Albonesi,
Steven Dropsho§, Juan Lanchares and Jose I. Hidalgo
Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA
slaeec@rit.edu
Department of Computer Architecture, Universidad Complutense de Madrid, Madrid, Spain
{ogarnica,julandan,hidalgo}@dacya.ucm.es
Computer Systems Laboratory, Cornell University, Ithaca, NY, USA
albonesi@csl.cornell.edu
§ Google Inc., Zurich, Switzerland
stevendropsho@google.com
Abstract--Resizable caches can trade-off capacity for ac-
cess speed to dynamically match the needs of the workload.
In Simultaneous Multi-Threaded (SMT) cores, the caching
needs can vary greatly across the number of threads and
their characteristics, offering opportunities to dynamically
adjust cache resources to the workload. In this paper we
propose the use of resizable caches in order to improve

Source: Albonesi, David H. - Computer Systems Laboratory, Cornell University

Collections: Computer Technologies and Information Sciences