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J Supercomput (2011) 55: 2850 DOI 10.1007/s11227-010-0396-0
 

Summary: J Supercomput (2011) 55: 28­50
DOI 10.1007/s11227-010-0396-0
Leakage-efficient design of value predictors through
state and non-state preserving techniques
Juan M. Cebrián · Juan L. Aragón ·
José M. García · Stefanos Kaxiras
Published online: 5 March 2010
© Springer Science+Business Media, LLC 2010
Abstract In the last decade computer engineers have faced changes in the way mi-
croprocessors are designed. New microprocessors do not only need to be faster than
the previous generation, but also be feasible in terms of energy consumption and
thermal dissipation. Recently, a new challenge appeared for computer engineers, the
static power consumption. As process technology advances toward deep submicron,
the static power component becomes a serious problem, especially for large on-chip
array structures such as caches or prediction tables, and it must be taken into consid-
eration. We can fight to reduce leakage power in two different ways: we can switch off
the structure, reducing its leakage to zero but losing its contents (non-state preserving
techniques), or we can lower its voltage (state preserving techniques), obtaining less
savings but being able to restore the state of the structure in a reasonable time.
Data dependences are one of the key factors that limit performance in modern

  

Source: Aragón Alcaraz, Juan Luis - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences