Summary: High-Level Design Verification of
Microprocessors via Error Modeling
DAVID VAN CAMPENHOUT, HUSSAIN AL-ASAAD,
JOHN P. HAYES, TREVOR MUDGE, and RICHARD B. BROWN
University of Michigan, Ann Arbor, Michigan
A design verification methodology for microprocessor hardware based on modeling design errors
and generating simulation vectors for the modeled errors via physical fault testing techniques is pre-
sented. We have systematically collected design error data from a number of microprocessor design
projects. The error data is used to derive error models suitable for design verification testing. A class
of basic error models is identified and shown to yield tests that provide good coverage of common
error types. To improve coverage for more complex errors, a new class of conditional error models is
introduced. An experiment to evaluate the effectiveness of our methodology is presented. Single
actual design errors are injected into a correct design, and it is determined if the methodology will
generate a test that detects the actual errors. The experiment has been conducted for two micropro-
cessor designs and the results indicate that very high coverage of actual design errors can be
obtained with test sets that are complete for a small number of synthetic error models.
Categories and Subject Descriptors: B.0 [Hardware] General --Design Aids; B.5.2 [Hardware]
Register-transfer-level implementation --Design Aids.
General Terms: Verification, microprocessors.
Additional Key Words and Phrases: Design verification, design errors, error modeling.