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Computer Science and Artificial Intelligence Laboratory Technical Report
 

Summary: Computer Science and Artificial Intelligence Laboratory
Technical Report
massachusetts institute of technology, cambridge, ma 02139 usa -- www.csail.mit.edu
MIT-CSAIL-TR-2007-003 January 11, 2007
Scale Control Processor Test-Chip
Chrstopher Batten, Ronny Krashinsky and
Krste Asanovic
Scale Control Processor Test-Chip
Christopher Batten, Ronny Krashinsky, and Krste Asanovi´c
Massachusetts Institute of Technology
Computer Science and Artificial Intelligence Laboratory
32 Vassar Street, 32-G736
Cambridge, MA 02139
January 5, 2007
We are investigating vector-thread architectures which provide competitive performance
and efficiency across a broad class of application domains [1, 4]. Vector-thread architectures
unify data-level, thread-level, and instruction-level parallelism, providing new ways of par-
allelizing codes that are difficult to vectorize or that incur excessive synchronization costs
when multithreaded. To illustrate these ideas we have developed the Scale processor, which
is an example of a vector-thread architecture designed for low-power and high-performance

  

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

 

Collections: Computer Technologies and Information Sciences