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A Hybrid Analytical DRAM Performance Model George L. Yuan Tor M. Aamodt
 

Summary: A Hybrid Analytical DRAM Performance Model
George L. Yuan Tor M. Aamodt
Department of Electrical and Computer Engineering
University of British Columbia, Vancouver, BC, CANADA
{gyuan,aamodt}@ece.ubc.ca
Abstract
As process technology scales, the number of transistors that
can fit in a unit area has increased exponentially. Proces-
sor throughput, memory storage, and memory throughput
have all been increasing at an exponential pace. As such,
DRAM has become an ever-tightening bottleneck for appli-
cations with irregular memory access patterns. Computer
architects in industry sometimes use ad hoc analytical mod-
eling techniques in lieu of cycle-accurate performance sim-
ulation to identify critical design points. Moreover, ana-
lytical models can provide clear mathematical relationships
for how system performance is affected by individual mi-
croarchitectural parameters, something that may be difficult
to obtain with a detailed performance simulator. Modern
DRAM controllers rely on Out-of-Order scheduling policies

  

Source: Aamodt, Tor - Department of Electrical and Computer Engineering, University of British Columbia

 

Collections: Engineering; Computer Technologies and Information Sciences