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Reducing Energy in Instruction Caches by Using Multiple Line Buffers with Prediction
 

Summary: Reducing Energy in Instruction Caches by Using
Multiple Line Buffers with Prediction
Kashif Ali Mokhtar Aboelaze Suprakash Datta
Department of Computer Science and Engineering
York University
Toronto ON CANADA
email: {kashif, aboelaze, datta}@cs.yorku.ca
Abstract-- Energy efficiency plays a crucial role in the design
of embedded processors especially for portable devices with its
limited energy source in the form of batteries. Since memory
access (either cache or main memory) consumes a significant
portion of the energy of a processor, the design of fast low-energy
caches has become a very important aspect of modern processor
design. In this paper, we present a novel cache architecture
for reduced energy instruction caches. Our proposed cache
architecture consists of the L1 cache, multiple line buffers, and a
prediction mechanism to predict which line buffer, or L1 cache
to access next. We used simulation to evaluate our proposed
architecture and compare it with the HotSpot cache, Filter cache,
Predictive line buffer cache and Way-Halting cache. Simulation

  

Source: Aboelaze, Mokhtar - Department of Computer Science, York University (Toronto)

 

Collections: Computer Technologies and Information Sciences