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A NOVEL EQUALISER ARCHITECTURE WITH DYNAMIC LENGTH OPTIMISATION
 

Summary: A NOVEL EQUALISER ARCHITECTURE WITH
DYNAMIC LENGTH OPTIMISATION
Mark P. Tennant*t, A.T. Erdogant, T. Arslant and J. Thompsont
tSchool of Engineering and Electronics, The University of Edinburgh
The King's Buildings, Edinburgh EH9 3JL
United Kingdom
*Email: M.P.Tennant@sms.ed.ac.uk
Abstract- This paper presents a novel architecture for tap- The technique of varying the length of the LMS filter was
length optimisation of the linear LMS equaliser. No analysis has first presented by the authors of [2] with an algorithm
previously been carried out to determine any tradeoff that exists which proved that a filter with fewer taps will have a faster
in circuit area against power saving achieved. A low-complexity
length update algorithm is employed to dynamically adjust and
optimise the number of taps in the linear equaliser according to This variable length stochastic gradient (VLSG) algorithm
channel conditions. The results show that the chosen algorithm demonstrates an LMS adaptive filter which can accomplish
presents minimal overhead and reduces power consumed due a change in its length from being initially low, therefore
to optimisation of the equaliser length. This paper presents the aiding fast convergence, gradually increasing over time to
first complete architectural VLSI implementation of the length a.idn
optimised equaliser and includes a performance study in terms achievthe low steady state MSE performance characteristic
of area and power. of higher order filters. In [3], Won et al. went on to propose
another variable length LMS (VL-LMS) algorithm using

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering