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Summary: AN EFFICIENT VERIFICATION METHOD
FOR A CLASS OF MULTI-PHASE SEQUENTIAL CIRCUITS
François-R. Boyer1
, El Mostapha Aboulhamid1
, and Yvon Savaria2
1
DIRO, Université de Montréal, 2920 Chemin de la Tour,
C.P. 6128, Succ. Centre-Ville, Montréal, Québec, Canada, H3C 3J7
{boyerf, aboulhamid}@IRO.Umontreal.CA
2
DGEGI, École Polytechnique de Montréal, Québec, Canada
savaria@VLSI.PolyMtl.CA
ABSTRACT: Currently, many optimizations of
sequential circuits, even as simple as retiming, are
avoided due to the lack of verification tools that support
them. Doing general sequential equivalence to compare
the circuits is impractical for circuits of a reasonable
size. On the other hand, combinational optimization is
part of the design process, because tools and methods
are available to ensure correctness and verify
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