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Domain-specific reconfigurable array for Distributed Arithmetic
 

Summary: Domain-specific reconfigurable array
for Distributed Arithmetic
Sami Khawam1
, Tughrul Arslan1,2
, Fred Westall3
1
School of Electronic and Engineering, The University of Edinburgh, KB,
Mayfield Road, Edinburgh EH9 3JL, UK, S.Khawam@ee.ed.ac.uk
2
Institute for System Level Integration, Livingston, EH54 7EG, UK
3
EPSON Scotland Design Centre, Livingston, EH54 7EG, UK
Abstract. Distributed Arithmetic techniques are widely used to implement Sum-of-Products
computations such as calculations found in multimedia applications like FIR filtering and Discrete
Cosine Transform. This paper presents a flexible, low-power and high throughput array for
implementing distributed arithmetic computations. Flexibility is achieved by using an array of
elements arranged in an interconnect mesh similar to those employed in conventional FPGA
architectures. We provide results which demonstrate a significant reduction in power consumption
in addition to improvements in timing and area over standard FPGA architectures.
Keywords: Embedded reconfigurable array, programmable, distributed arithmetic, FPGA, domain

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering