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Summary: 1
Abstract--We survey a set of flip-flops designed for low
power and high performance. We highlight the basic fea-
tures of these flip-flops and evaluate them based on timing
characteristics, power consumption, and other metrics.
1 INTRODUCTION
Low power consumption has become a highly impor-
tant design concern in this era and will become more and
more important as we move to all mobile computing and
communications. The transistor density of IC is growing at
Moore's law rate and the incomparable battery advances
will mandate lower power methodologies and designs.
Most of the current designs are synchronous which
implies that flip-flops and latches are involved in one way
or another in the data and control paths. One of the chal-
lenges of low power methodologies for synchronous sys-
tems is the power consumption of these flip-flops and
latches. It is important to save power in these flip-flops and
latches without compromising state integrity or perfor-
mance.
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