Summary: Scalable Thread Scheduling and Global Power
Management for Heterogeneous Many-Core Architectures
Jonathan A. Winter
Google Inc.
Mountain View, CA
jawinter@google.com
David H. Albonesi
Computer Systems Laboratory
Cornell University, Ithaca, NY
albonesi@csl.cornell.edu
Christine A. Shoemaker
CEE, Applied Math, & ORIE
Cornell University, Ithaca, NY
cas12@cornell.edu
ABSTRACT
Future many-core microprocessors are likely to be heterogeneous,
by design or due to variability and defects. The latter type of
heterogeneity is especially challenging due to its unpredictability.
To minimize the performance and power impact of these
hardware imperfections, the runtime thread scheduler and global

Source: Albonesi, David H. - Computer Systems Laboratory, Cornell University
Pregibon, Daryl - Google Labs

Collections: Computer Technologies and Information Sciences; Mathematics