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Summary: Exploiting address compression and heterogeneous interconnects for efficient
message management in tiled CMPs
Antonio Flores *, Manuel E. Acacio, Juan L. Aragón
Departamento de Ingeniería y Tecnología de Computadores, University of Murcia, 30100 Murcia, Spain
a r t i c l e i n f o
Article history:
Received 2 December 2008
Received in revised form 27 April 2010
Accepted 7 May 2010
Available online 19 May 2010
Keywords:
Tiled chip multiprocessor
Energy-efficient architecture
Cache-coherence protocol
Heterogeneous on-chip interconnection
network
a b s t r a c t
High performance processor designs have evolved toward architectures that integrate multiple process-
ing cores on the same chip. As the number of cores inside a Chip MultiProcessor (CMP) increases, the
interconnection network will have significant impact on both overall performance and energy consump-
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