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Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams

Summary: Evaluation of the Raw Microprocessor:
An Exposed-Wire-Delay Architecture for ILP and Streams
Michael Bedford Taylor, Walter Lee, Jason Miller, David Wentzlaff,
Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota,
Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank,
Saman Amarasinghe, and Anant Agarwal
CSAIL, Massachusetts Institute of Technology
This paper evaluates the Raw microprocessor. Raw addresses the
challenge of building a general-purpose architecture that performs
well on a larger class of stream and embedded computing appli-
cations than existing microprocessors, while still running existing
ILP-based sequential programs with reasonable performance in the
face of increasing wire delays. Raw approaches this challenge by
implementing plenty of on-chip resources including logic, wires,
and pins in a tiled arrangement, and exposing them through a new
ISA, so that the software can take advantage of these resources for
parallel applications. Raw supports both ILP and streams by rout-
ing operands between architecturally-exposed functional units over
a point-to-point scalar operand network. This network offers low


Source: Amarasinghe, Saman - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)


Collections: Computer Technologies and Information Sciences