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Summary: On the Construction of Zero-Deficiency
Parallel Prefix Circuits with Minimum Depth
HAIKUN ZHU, CHUNG-KUAN CHENG, and RONALD GRAHAM
University of California, San Diego
A parallel prefix circuit has n inputs x1, x2, . . . , xn, and computes the n outputs yi = xi · xi-1 · · · · ·
x1, 1 i n, in parallel, where · is an arbitrary binary associative operator. Snir proved that the
depth t and size s of any parallel prefix circuit satisfy the inequality t +s 2n-2. Hence, a parallel
prefix circuit is said to be of zero-deficiency if equality holds. In this article, we provide a different
proof for Snir's theorem by capturing the structural information of zero-deficiency prefix circuits.
Following our proof, we propose a new kind of zero-deficiency prefix circuit Z(d) by constructing
a prefix circuit as wide as possible for a given depth d. It is proved that the Z(d) circuit has the
minimal depth among all possible zero-deficiency prefix circuits.
Categories and Subject Descriptors: B.6.1 [Logic Design]: Design Styles--Parallel circuits
General Terms: Algorithms, Design, Theory
Additional Key Words and Phrases: Zero-deficiency, parallel prefix circuits, depth-size trade-off
1. INTRODUCTION
1.1 Problem Definition
The prefix problem, which mostly gains research attention with the emergence
of parallel computing, is actually the abstraction of many practical applications
such as binary addition, radix sort, linear recurrences solving, polynomial eval-
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