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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006 433 Process and Temperature Compensation in a 7-MHz
 

Summary: IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006 433
Process and Temperature Compensation in a 7-MHz
CMOS Clock Oscillator
Krishnakumar Sundaresan, Student Member, IEEE, Phillip E. Allen, Life Fellow, IEEE, and
Farrokh Ayazi, Senior Member, IEEE
Abstract--This paper reports on the design and characterization
of a process, temperature and supply compensation technique for
a 7-MHz clock oscillator in a 0.25- m, two­poly five-metal (2P5M)
CMOS process. Measurements made across a temperature range
of 40 C to 125 C and 94 samples collected over four fabrica-
tion runs indicate a worst case combined variation of 2.6% (with
process, temperature and supply). No trimming was performed on
any of these samples. The oscillation frequencies of 95% of the sam-
ples were found to fall within 0.5% of the mean frequency and the
standard deviation was 9.3 kHz. The variation of frequency with
power supply was 0.31% for a supply voltage range of 2.4­2.75
V. The clock generator is based on a three-stage differential ring
oscillator. The variation of the frequency of the oscillator with tem-
perature and process has been discussed and an adaptive biasing
scheme incorporating a unique combination of a process corner

  

Source: Ayazi, Farrokh - School of Electrical and Computer Engineering, Georgia Institute of Technology

 

Collections: Engineering