Summary: Journal of Instruction­Level Parallelism 2 (2000) 1­16 Submitted 2/00; published 5/00
Code Transformations to Improve Memory Parallelism \Lambda
Vijay S. Pai VIJAYPAI@ECE.RICE.EDU
Electrical and Computer Engineering -- MS 366, Rice University
Houston, TX 77005 USA
Sarita Adve SADVE@CS.UIUC.EDU
Computer Science, University of Illinois
Urbana­Champaign, IL 61801 USA
Abstract
Current microprocessors incorporate techniques to exploit instruction­level parallelism (ILP). However,
previous work has shown that these ILP techniques are less effective in removing memory stall time than
CPU time, making the memory system a greater bottleneck in ILP­based systems than in previous­generation
systems. These deficiencies arise largely because applications present limited opportunities for an out­of­
order issue processor to overlap multiple read misses, the dominant source of memory stalls.
This work proposes code transformations to increase parallelism in the memory system by overlapping
multiple read misses within the same instruction window, while preserving cache locality. We present an
analysis and transformation framework suitable for compiler implementation. Our simulation experiments
show execution time reductions averaging 20% in a multiprocessor and 30% in a uniprocessor. A substantial
part of these reductions comes from increases in memory parallelism. We see similar benefits on a Convex
Exemplar.

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign

Collections: Computer Technologies and Information Sciences