Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
An Efficient Cache Design for Scalable Glueless Shared-Memory Multiprocessors
 

Summary: An Efficient Cache Design for Scalable Glueless
Shared-Memory Multiprocessors
Alberto Ros
a.ros@ditec.um.es
Manuel E. Acacio
meacacio@ditec.um.es
Jos´e M. Garc´ia
jmgarcia@ditec.um.es
Departamento de Ingenier´ia y Tecnolog´ia de Computadores
Universidad de Murcia
30080 Murcia (Spain)
ABSTRACT
Traditionally, cache coherence in large-scale shared-memory
multiprocessors has been ensured by means of a distributed
directory structure stored in main memory. In this way,
the access to main memory to recover the sharing status of
the block is generally put in the critical path of every cache
miss, increasing its latency. Considering the ever-increasing
distance to memory, these cache coherence protocols are far
from being optimal from the perspective of performance. On

  

Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences