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Maintaining Digital Clocks In Step Anish ARORA 1 Shlomi DOLEV 2 Mohamed GOUDA 1

Summary: Maintaining Digital Clocks In Step
Anish ARORA 1 Shlomi DOLEV 2 Mohamed GOUDA 1
1. Department of Computer Sciences, The University of Texas at Austin, USA
2. Department of Computer Science, Technion, ISRAEL
A system of simultaneously triggered clocks is designed to be stabilizing: if the
clock values ever differ, the system is guaranteed to converge to a state where all
clock values are identical, and are subsequently maintained to be identical. For an
N­clock system, the design uses N registers of 2 log N bits each and guarantees con­
vergence to identical values within N 2 ``triggers''.
Keywords: stabilization, reliability, distributed algorithms, digital clocks, conver­
1 Introduction
Digital systems are often designed to be synchronous; that is, a system­wide clock pulse
is used to ensure that system parts operate in ``lock­step''. One building block that is
commonly used in the design of such systems is a digital clock. Operationally, the task
of a digital clock is to maintain a count of the number of clock pulses as they occur.
The use of digital clocks in circuit design is frequent; for example,
ffl Synchronization : A circuit may include some parts that need to synchronize with
other parts periodically [1]. The periods, in this case, can be measured using a


Source: Arora, Anish - Department of Computer Science and Engineering, Ohio State University
Dolev, Shlomi - Department of Computer Science, Ben-Gurion University


Collections: Computer Technologies and Information Sciences