Summary: Appears in: The 2002 Symposium on VLSI Circuits, Honolulu, HI, June 2002
Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction £
Seongmoo Heo and Krste Asanovi´c
MIT Laboratory for Computer Science
200 Technology Square
Cambridge, MA 02139
heomoo,krste @lcs.mit.edu
Abstract
A Leakage-Biased Domino circuit family is proposed that main-
tains high speed in active mode but which can be rapidly placed
into a low-leakage inactive state by using leakage currents them-
selves to bias internal nodes. A 32-bit Han-Carlson domino adder
circuit is used to compare LB-Domino with conventional single and
dual Vt domino circuits. For equal delay and noise margin, the
LB-Domino technique gives two decades reduction in steady-state
leakage energy compared to a dual-Vt technique.
Introduction
Energy dissipation has emerged as the primary design constraint
for many systems, from portable electronics to high-performance
microprocessors. Until recently, the dominant cause of energy dis-

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

Collections: Computer Technologies and Information Sciences