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Phastlane: A Rapid Transit Optical Routing Network Mark J. Cianchetti, Joseph C. Kerekes, and David H. Albonesi
 

Summary: Phastlane: A Rapid Transit Optical Routing Network
Mark J. Cianchetti, Joseph C. Kerekes, and David H. Albonesi
Computer Systems Laboratory
Cornell University
{mjc96,jck46,dha7}@cornell.edu
ABSTRACT
Tens and eventually hundreds of processing cores are projected
to be integrated onto future microprocessors, making the global
interconnect a key component to achieving scalable chip perfor-
mance within a given power envelope. While CMOS-compatible
nanophotonics has emerged as a leading candidate for replacing
global wires beyond the 22nm timeframe, on-chip optical intercon-
nect architectures proposed thus far are either limited in scalability
or are dependent on comparatively slow electrical control networks.
In this paper, we present Phastlane, a hybrid electrical/optical
routing network for future large scale, cache coherent multicore
microprocessors. The heart of the Phastlane network is a low-
latency optical crossbar that uses simple predecoded source routing
to transmit cache-line-sized packets several hops in a single clock
cycle under contentionless conditions. When contention exists, the

  

Source: Albonesi, David H. - Computer Systems Laboratory, Cornell University

 

Collections: Computer Technologies and Information Sciences