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Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance
 

Summary: Exploiting Coarse-Grain Verification Parallelism for
Power-Efficient Fault Tolerance
M. Wasiur Rashid, Edwin J. Tan, and Michael C. Huang
Department of Electrical & Computer Engineering
University of Rochester
{rashid, etan, michael.huang}@ece.rochester.edu
David H. Albonesi
Computer Systems Laboratory
Cornell University
albonesi@csl.cornell.edu
Abstract
As device dimensions continue to be aggressively scaled, mi-
croprocessors are becoming increasingly vulnerable to the impact
of undesired energy, such as that of a cosmic particle strike, which
can cause transient errors. To prevent operational failure due to
these errors, system-level techniques such as redundant execution
will be increasingly required for fault detection and tolerance in
future processors. However, the need for redundancy is directly
opposed to the growing need for more power efficient operation.
Conventional techniques that use multi-core microarchitectures to

  

Source: Albonesi, David H. - Computer Systems Laboratory, Cornell University
Huang, Michael C. - Department of Electrical and Computer Engineering, University of Rochester

 

Collections: Computer Technologies and Information Sciences