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Micronetbased CISC Architectures D. K. Arvind and C. Bainbridge

Summary: Micronet­based CISC Architectures
D. K. Arvind and C. Bainbridge
Institute for Computing Systems Architecture
Division of Informatics, University of Edinburgh
Mayfield Road, Edinburgh EH9 3JZ, Scotland.
Email: dka@dcs.ed.ac.uk
We have in the past investigated the design and implementation of micronet­based architectures of the scalar[AR94],
superscalar[AM99], VLIW[AS97] and Multithreaded[AHKR01] kind, which were all based on a RISC­like instruction set.
In this paper, we present a preliminary design, based around a micronet core, of an asynchronous Complex Instruction
Set Computer (CISC) architecture. A TRANSLATOR module converts the CISC instructions into ones which are native to
the micronet datapath, called the milliops instructions. This translation can be accomplished either in hardware, as in
Intel's x86 architectures, or in software, in the style of Transmeta's Crusoe architecture. The design environment enables C
programs targeted at the CISC architecture, to be executed on a RTL model of the micronet core, and its execution and power
consumption can be visualised over space and time. This allows a systematic study of the effect of compiler and architectural
optimisations of micronet­based CISC processors, on the performance of application benchmarks.
1 Introduction
We aim to develop high­performance, low­power programmable SOC cores. We seek high performance, by exploiting the
available concurrency in the applications, and low power, through the asynchronous implementation of the SOC cores. The
core architecture combines computational structures such as micronets or networks­on­a­chip, with software programmabil­


Source: Arvind, D. K. - School of Informatics, University of Edinburgh


Collections: Computer Technologies and Information Sciences