Summary: Two Adaptive Hybrid Cache Coherency Protocols
Craig Anderson Anna R. Karlin
Apple Computer Dept. of Computer Science and Engineering
1 Infinite Loop, MS 301­4G University of Washington
Cupertino, CA 95014 Seattle, WA 98195­2350
Abstract
We present and evaluate adaptive, hybrid cache co­
herence protocols for bus­based, shared­memory mul­
tiprocessors. Such protocols are motivated by the ob­
servation that sharing patterns vary substantially be­
tween different programs and even cache blocks within
the same program. Performance measurements across
a range of parallel applications indicate that the adap­
tive protocols we present perform well compared to both
Write­Invalidate and Write­Update protocols.
1 Introduction
In a bus­based multiprocessor, bus contention can
lead to increased program execution time because a
processor may stall while its cache is waiting for the
bus. For many interesting applications, the bus trans­

Source: Anderson, Richard - Department of Computer Science and Engineering, University of Washington at Seattle

Collections: Computer Technologies and Information Sciences