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Appears in IEEE International High Level Design Validation and Test Workshop, November 2007 Transactors for Parallel Hardware and Software Co-Design
 

Summary: Appears in IEEE International High Level Design Validation and Test Workshop, November 2007
Transactors for Parallel Hardware and Software Co-Design
Krste Asanovi´c
Computer Science Division
University of California at Berkeley
krste@eecs.berkeley.edu
1 Introduction
Complex, high-performance, low-power information pro-
cessing systems usually incorporate a mixture of hardware
and software elements, and pose significant design chal-
lenges. Conventional register-transfer level (RTL) hardware
design methodologies are too low-level, requiring designs to
be partitioned into collections of combinational gates sepa-
rated by clocked registers. Conversely, threaded parallel soft-
ware design methodologies provide a very high-level speci-
fication from which it is difficult to synthesize efficient gate-
level implementations. In this paper, we introduce the trans-
actor (transactional actor) model to provide a natural level
of design representation for both hardware and software im-
plementation. As shown in Fig. 1, a design is modeled as a

  

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

 

Collections: Computer Technologies and Information Sciences