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Abstract--We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax
 

Summary: Abstract-- We present a new multi-rate architecture for
decoding irregular LDPC codes in IEEE 802.16e WiMax
standard. The proposed architecture utilizes the value­reuse
property of offset min-sum, block-serial scheduling of
computations and turbo decoding message passing algorithm.
The decoder has the following advantages: 55% savings in
memory, reduction of routers by 50%, and increase of
throughput by 2x when compared to the recent state-of-the-art
decoder architectures.
Index Terms-- low-density parity-check (LDPC) codes, offset
min-sum, on-the-fly computation, decoder architecture, layered
decoding, turbo-decoding message passing, irregular
LDPC,IEEE 802.16e.
I. INTRODUCTION
Low-Density Parity-Check (LDPC) codes and turbo codes
are among the known near Shannon limit codes that can
achieve very low bit error rates for low signal-to-noise ratio
(SNR) applications [1]. When compared to the decoding
algorithm of Turbo codes, LDPC decoding algorithm has more
parallelization, low implementation complexity, low decoding

  

Source: Atiquzzaman, Mohammed - School of Computer Science, University of Oklahoma

 

Collections: Computer Technologies and Information Sciences