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A General Approach to Deadlock Freedom Veri cation

Summary: A General Approach
to Deadlock Freedom Veri cation
for Software Architectures
Alessandro Aldini and Marco Bernardo
Universita di Urbino \Carlo Bo"
Istituto di Scienze e Tecnologie dell'Informazione
Piazza della Repubblica 13, 61029 Urbino, Italy
faldini, bernardog@sti.uniurb.it
Abstract. When building complex software systems, the designer is
faced with the problem of detecting mismatches arising from the activity
of assembling components. The adoption of formal methods becomes un-
avoidable in order to support a precise identi cation of such mismatches
in the early design stages. As far as deadlock freedom is concerned, some
techniques appeared in the literature, which apply to formal speci ca-
tions of software architectures under some constraints. In this paper we
develop a novel technique for deadlock freedom veri cation that can be
applied to arbitrary software architectures, thus overcoming the limita-
tions of the previous techniques.
Keywords: software architecture, deadlock, process algebra.
1 Introduction


Source: Aldini, Alessandro - Dipartimento di Matematica, Fisica e Informatica, Universita’ di Urbino "Carlo Bo"


Collections: Computer Technologies and Information Sciences