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Phase-Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology
 

Summary: Phase-Locked Loop with Leakage and Power/Ground
Noise Compensation in 32nm Technology
Kyung Ki Kim, Yong-Bin Kim
Department of Electrical and Computer Engineering
Northeastern University
Boston, USA
{kkkim, ybk}@ece.neu.edu
Young Jun Lee
NextChip Corp.
Seoul, Korea
yjlee@nextchip.com
Abstract - This paper presents two novel compensation
circuits for leakage current and power supply noise
(PSN) in phase locked loop (PLL) using a nanometer
CMOS technology. The leakage compensation circuit
reduces the leakage current of the charge pump circuit
and the PSN compensation circuit decreases the effect of
power supply variation on the output frequency of VCO.
The PLL design is based on a 32nm predictive CMOS
technology and uses a 0.9 V power supply voltage. The

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering