Summary: Modeling a Reconfigurable System for Computing the FFT in Place via
Rewriting­Logic #
Mauricio Ayala­Rincón 1,* , Rodrigo B. Nogueira §,2,* , Carlos H. Llanos 2,* , Ricardo P. Jacobi 3,* ,
Reiner W. Hartenstein 4,+
Departamentos de 1 Matemática, 2 Engenharia Mecânica, 3 Ciência da Computação, * Universidade
de Brasília, 4 Fachbereich Informatik, + Universität Kaiserlautern
ayala@mat.unb.br, llanos@unb.br, rjacobi@cic.unb.br, rhartenst@rhrk.uni­kl.de
# Work supported by the CAPES­DFG Brazilian­German foundations.
§ Author partially supported by the CNPq Brazilian council.
Abstract
The growing adoption of reconfigurable architectures
opens new implementation alternatives and creates new
design challenges. In the case of dynamically
reconfigurable architectures, the choice of an efficient
architecture and reconfiguration scheme for a given
application is a complex task. Tools for exploration of
design alternatives at higher abstraction levels are needed.
This paper describes the modeling and simulation of a
dynamically reconfigurable hardware implementation of
the Fast Fourier Transform -- FFT using rewriting­logic. It

Source: Ayala-Rincón, Mauricio - Departamento de Matemática, Universidade de Brasília

Collections: Mathematics