| | |
Summary: Assessing SEU Vulnerability
via Circuit-Level Timing Analysis
Kypros Constantinides Stephen Plaza Jason Blome Bin Zhang1
Valeria Bertacco Scott Mahlke Todd Austin Michael Orshansky1
Advanced Computer Architecture Lab 1
Department of Electrical and Computer Engineering
University of Michigan University of Texas at Austin
Ann Arbor, MI 48109 Austin, TX, 78712
{kypros, splaza, jblome, valeria, bzhang@ece.utexas.edu
mahlke, austin}@umich.edu orshansky@mail.utexas.edu
ABSTRACT
Recently, there has been a growing concern that, in relation
to process technology scaling, the soft-error rate will become
a major challenge in designing reliable systems. In this
work, we introduce a high-fidelity, high-performance simu-
lation infrastructure for quantifying the derating effects on
soft-error rates while considering microarchitectural, tim-
ing and logic-related masking, using realistic workloads on
a CMP switch design. We use a gate-level model for the
CMP switch design, enabling us to inject faults into blocks of
|
