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A Low-offset High-speed Double-tail Dual-rail Dynamic Latched Comparator
 

Summary: A Low-offset High-speed Double-tail Dual-rail Dynamic
Latched Comparator
HeungJun Jeon and Yong-Bin Kim
Department of Electrical and Computer Engineering
Northeastern University
Boston, MA, USA
hjeon@ece.neu.edu and ybk@ece.neu.edu
ABSTRACT
This paper presents a new dynamic latched comparator which
shows lower input-referred latch offset voltage and higher load
drivability than the conventional dynamic latched comparators.
With two additional inverters inserted between the input- and
output-stage of the conventional double-tail dynamic comparator,
the gain preceding the regenerative latch stage was improved and
the complementary version of the output-latch stage, which has
bigger output drive current capability at the same area, was
implemented. As a result, the circuit shows up to 25% less input-
referred latch offset voltage and 44% less sensitivity of the delay
versus the input voltage difference (delay/log(!Vin)), which is
about 17.2ps/decade, than the conventional double-tail latched

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering