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A Novel CNTFET-Based Ternary Logic Gate Sheng Lin, Yong-Bin Kim and Fabrizio Lombardi
 

Summary: A Novel CNTFET-Based Ternary Logic Gate
Design
Sheng Lin, Yong-Bin Kim and Fabrizio Lombardi
Department of Electrical and Computer Engineering
Northeastern University
Boston, MA, USA
Abstract--This paper presents a novel design of ternary
logic inverters using carbon nanotube FETs (CNTFETs).
Multiple-valued logic (MVL) circuits have attracted
substantial interest due to the capability of increasing
information content per unit area. In the past extensive
design techniques for MVL circuits (especially ternary logic
inverters) have been proposed for implementation in CMOS
technology. In CNTFET device, the threshold voltage of the
transistor can be controlled by controlling the chirality
vector (i.e. the diameter); in this paper this feature is
exploited to design ternary logic inverters. New designs are
proposed and compared with existing CNTFET-based
designs. Extensive simulation results using SPICE
demonstrate that power delay product is improved by 300%

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering